The present invention relates to non-volatile memory devices and methods of manufacturing the same. More particularly, the present invention relates to non-volatile memory devices including a charge-trapping layer and methods of manufacturing the same.
Integrated circuit (e.g., semiconductor) memory devices are generally classified as either volatile or non-volatile memory devices. Volatile memory devices, such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices, have relatively high input/output (I/O) speeds. However, volatile semiconductor memory devices lose data stored therein when power is shut off. On the other hand, although non-volatile memory devices, such as electrically erasable programmable read-only memory (EEPROM) devices and/or flash memory devices, typically have relatively slow I/O speeds, non-volatile memory devices are able to maintain data stored therein even when power is shut off.
In EEPROM devices, data is electrically stored, i.e., programmed or erased through a Fowler-Nordheim (F-N) tunneling mechanism and/or a channel hot electron injection mechanism. Flash memory devices are generally classified as either a floating gate type or a charge trap type, such as silicon-oxide-nitride-oxide semiconductor (SONOS) type devices or metal-oxide-nitride-oxide semiconductor (MONOS) type devices.
The charge trap type non-volatile memory device typically includes a tunnel insulating layer formed on a channel region of a semiconductor substrate, a charge-trapping layer for trapping electrons from the channel region, a dielectric layer formed on the charge-trapping layer, a gate electrode formed on the dielectric layer, spacers formed on sidewalls of the gate electrode and source/drain regions formed at surface portions of the semiconductor substrate adjacent to the channel region.
When thermal stress is applied to the charge trap type non-volatile memory device, electrons trapped in the charge-trapping layer may be laterally diffused, which may deteriorate high-temperature stress (HTS) characteristics of the non-volatile memory device. For example, when a non-volatile memory device is maintained at a temperature of about 200° C. for about 2 hours, the threshold voltage of the non-volatile memory device may be significantly reduced. For example, when programming and erasing operations of a non-volatile memory device are repeatedly performed about 1,000 to about 1,200 times, and the non-volatile memory device is then maintained at a temperature of about 200° C. for about 2 hours, the threshold voltage of the non-volatile memory device may be significantly reduced.
To limit the lateral diffusion of electrons, portions of the charge-trapping layer between memory cells may be removed. However, it is difficult to control an etching process for partially removing the portions of the charge-trapping layer because an etching selectivity between a silicon nitride layer serving as the charge-trapping layer and a silicon oxide layer serving as the tunnel insulating layer is typically small and the charge-trapping layer is generally very thin. Further, the tunnel insulating layer may be damaged while etching the charge-trapping layer.